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E1 transceiver
Fully synchronous implementation of complete E1 line (2048 kbit/s) transmitter and receiver. Includes: • HDB-3 codec (for electric interface) • CMI codec (for optical interface) • Clock recovery module • Framer and super-frame framer • Synchronization module for framse and superframes • Generating and checking CRC-4 check sum • Simplified version for E2 line (8448 kbit/s) availabe Block diagram 
Description Using clock signal (clk), transmitter clocks slopes (tx_clk_ena, tx_clk2_ena), data line (tx_data) and bit number (tx_bit_numer[11..0]), coded signal is being sent to line transmitter (tx_B[1..0]) or optical trasmitter (tx_opto). Transmitter modules fills only timeslot 0, other slots are filled with bits from data input line (tx_data). CRC_enable line, enables or disables CRC-4 generation and checking. The receiver, receives signals from electric interface comparators (rx_B[1..0]) or optical intrface (rx_opto). Clock recovery module, generates clock impulses (rx_clk_ena, rx_clk2_ena) and detected data signal (rx_data). Frame and superframe receiver generates number of bit in frame and superframe (rx_bit_number[]) for each rx_data bit. The frame receiver also generate diagnostic and alarm signals: loss of signal (AIS), synchronization state (sync[]), and CRC-4 errors (rx_E[]). Application examples: V5.2 ISDN Access Node ISDN-IP gateway DSTG gateways USB Endpoint Optical Converter KOE-4 AWP-IŁ Communication Device MSB-2 Bit Error Rate Meter |