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HDLC protocol controller
Fully synchronous, bit oriented implementation of HDLC controller, capable of: • Inserting and removing flags • Bitstuffing "0" in long series of "1" • Inserting and detecting "abort" sequences • Generating and verifing CRC check sum • Full duplex • Buffering transmitted and received data in FIFO registers • 8 or 16 bit interface towards uProcessor • Interface to USB bus and Linux module driver available Block diagram 
Description The transmitter takes succesive bytes from internal buffers and sends them on tx_data lines, with speed of tx_clk_ena clock. Long series of "1" are stuffed with "0"-s (according to HDLC standard). After full frame, CRC check sum is being automaticaly send. Gaps between frames are stuffed with flag bytes "01111110". The receiver, receives succesive bits from rx_data line, with speed of rx_clk_ena clock, and puts them into internal buffer (after removing bitstuffing and CRC checking), which is available through FIFO. Buses: tx_bit[], tx_slot, rx_bit[] i rx_slot allow configuring time slots (may be different for receiving and transmitting) in which HDLC frames are transmitted. The controller can be connected to host uProcessor as memory mapped peripherial device (8, or 16 bit data bus). FIFOs level may be reported to uP by masked interrupts. Application examples: V5.2 ISDN Access Node ISDN-IP gateway DSTG gateways USB Endpoint AWP-IŁ Communication Device |