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ATM cells transceiver
Function implements ATM cells transceiver in cell-based system. It includes: • ATM transmitter • ATM receiver with header error correction • Scrambler enabling/disabling • universal FIFO buffers interface for sending and reception Block diagram 
Description Transmitter Data (txData) for PHD line framer is sent with clock signal (TxClkEna) in selected time slots (choosen by TxBitNumber[]). Active state of emptyCell line means that output FIFO buffer is empty and empty cells are being automatically sent. If FIFO buffer contains cells to send, successive bytes of the cell are passed by din[] bus (byte number is sent on txByteAddr[] bus) on request signal (txByteRq) and acknowledge signal (txByteAck) slopes. Transmitter automaticaly inserts HEC (header error control) and optionally scrambles cell's information field. Receiver PHD framer deliveres data to receiver (rxData line) with its number in frame (rxBitNumber[]) on clock signal slopes (rxClkEna). Receiver recovers cell synchronization basing on headers CRC. Receiver automatically corrects single header errors. Header and information field bytes are bassed to FIFO buffer using dout[] bus on request (rxByteRq) and acknowledge signals (rxByteAck). RxByteAddr[] bus value points position of current byte in cell. RxCellSync[] and rxCellInfo[] outputs inform about synchronization status of cell receiver, type of cell being received and HEC errors. FIFO buffers We have prepared functions implementing FIFO buffers for data sending and receipt. |