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Broadband multilevel QAM demodulator
Complete multi-level QAM demodulator for digital signal reception, implemented in digital signal processing technique in programmable device (FPGA). Analog signal (at intermediate frequency) is converted by fast ADC to digital samples. Rest of processing s implemented as digital signal processing, which allows to achive signal parameters, impossible to achive using different technologies. Block diagram 
Analog signal (at intermediate frequency) is converted by fast ADC to digital samples. Rest of processing: carrier recovery, clock recovery, demodulation, filtration, correction is realized by digital signal processing. All the receiver's blocks have been implemented in programmable logic device (FPGA). Output of the receiver consist of binary digital data (RxS) and recovered clock (RxC). The receiver also provides information about signal parameters, for example Quality. There is also possibility to observe received signal eye pattern, which shows signal's quality and distortions. Pictures on the right side show eye pattern of recevied QAM signal (top picture), and input signal at intermediate frequency (10.7 MHz). Transmission speed is 9126 kbit/s at 2304 kbaud modulation (QAM16). |