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DSP - technologies for signal processors DSP - technologies for programmable devices Telecommunication modules in programmable devices E1 tranceiver (G.703/G.704) HDLC protocol controller Fully programmable digital phase loops (with fully programmable parameters) ATM/B-ISDN: transceiver G.804 cells ATM/B-ISDN: cell-based transceiver I.432.1 cells Plesiochronous 4xE1 multiplex/demultiplex STANAG 4206 EUROCOM/D1 transceiver Embedded applications	ATM cells transceiver for PHD line Function implements ATM cells transceiver for PDH line, including:    • ATM cells transmitter in selected PDH line timeslots    • ATM cells receiver with header correction    • Scrambler enable/disable option    • IMA protocol controller support:       • IMA frame generation       • ICP cells insertion       • ICP cells sending and reception (by seperate interface)    • Universal FIFO buffers interface for sending, reception and ICP protocol controller Block diagram Description Transmitter     Data (txData) for PHD line framer are sent with clock signal (TxClkEna) in selected time slots (choosen by TxBitNumber[]). Active state of emptyCell line means that output FIFO buffer is empty and empty cells (or filler cells for IMA protocol) are being automatically sent. If FIFO buffer contains cells to send, successive bytes of the cell are passed by lin[] bus (byte number is sent on txByteAddr[] bus) on request signal (txByteRq) and acknowledge signal (txByteAck) slopes. If IMA mode is active (IMA_enable line active), then IPC control cell is passed on txIMA_ICPbyteRq slopes. Transmiter counts CRC-10 control sum for IMA cells, automaticaly inserts HEC (header error control) and optionally scrambles cell's information field. Receiver     PHD framer deliveres data to receiver (rxData line) with its number in frame (rxBitNumber[]) on clock signal slopes (rxClkEna). Receiver recovers cell synchronization basing on headers CRC. Receiver automatically corrects single header errors. Header and information field bytes are bassed to FIFO buffer using dout[] bus on request (rxByteRq) and acknowledge signals (rxByteAck). RxByteAddr[] bus value points position of current byte in cell. If receive is in IMA mod (IMA_enable line is active), then filler cells of IMA protocol are discarded and ICP cells are put to receive buffer of IMA protocol controller. RxCellSync[] and rxCellInfo[] outputs inform about synchronization status of cell receiver, type of cell being received and HEC errors. FIFO buffers and IMA protocol controller     We have prepared functions implementing FIFO buffers for sending, receipt and for IMA controller, that executes low level procedures of IMA 1.0 and 1.1 protocol.