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Broadband FM demodulator
Complete binary frequency modulation receiver, implemented in DSP technique, in programmable logic device (FPGA). Analog signal (at intermediate frequency) is converted by fast ADC to digital samples. Rest of processing s implemented as digital signal processing, which allows to achive signal parameters, impossible to achive using different technologies. Block diagram 
Analog signal (at intermediate frequency) is converted by fast ADC to digital samples. Rest of processing: filtration, frequency selection, demodulation, post-modulation filtraion and clock recovery is realized by digital signal processing. All the receiver's blocks have been implemented in programmable logic device (FPGA). Output of the receiver consist of binary digital data (RxD) and recovered clock (RxC). The receiver also provides information about signal parameters, for example Quality. There is also possibility to observe received signal eye pattern, which shows signal's quality and distortions. The receiver also implements module for 16 kbit/s EOW channel signal recovery. Picture below shows ey pattern of received digital signal of following bit rates: 2304 kbit/s, 1152 kbit/s, 567 kbit/s, 288 kbit/s 
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